Easier multi-device coordination: RISC-V facilitates better coordination among multiple edge devices through its open ...

Talk of RISC-V hitting 25% market penetration has been doing the rounds this week, with recent moves by Meta and Qualcomm often cited as evidence that the instruction set is moving beyond hobbyist ...

Bao Yungang, vice director of the Chinese Academy of Sciences' Institute of Computing Technology and chief scientist at the Beijing Open Source Chip Academy, predicts RISC-V will become the world's ...

New Espressif microcontrollers unveiled at CES 2026 include the tri-band Wi-Fi 6E ESP32-E22 and ultra-low-power ESP32-H21.

The nRF54LM20B SoC pairs the Axon NPU with 2 MB NVM, 512 KB RAM, a 128 MHz Arm Cortex-M33 plus RISC-V coprocessor, high-speed ...

Nordic Semi nRF54ML20B Arm Cortex-M33 wireless SoC is the first nRF54L microcontroller to integrate the ultra-efficient Axon ...

NASA’s future missions face sabotage risks from China’s tech strategy. Leaders must act now—or risk losing the space race for ...

Espressif Systems is showcasing its products at CES 2026, including two interesting upcoming parts: the ESP32-E22 Wi-Fi 6E ...

Elektor is seeking presentations for its online conference on RISC-V on April 15, 2026. The call for presentations is open ...

MIPS unveiled AI neural processor intellectual property based on RISC-V at CES, intended to support transformer and agentic language AI models at the edge.

As AI drives demand for advanced computing infrastructure, chip architectures are at a crossroads. While proprietary instruction set architectures (ISAs) like x86 and Arm dominate the market, their ...