The huge undertaking of verifying a system-on-chip (SoC) design has challenged engineers for more than 20 years –– the amount of time spent on it hasn’t varied much from between 50-70% of the entire ...

Every design verification technique requires coverage metrics to gauge progress, assess effectiveness, and help determine when the design is robust enough for tapeout. At every step of the way and ...

For years the process of ASIC and FPGA design and verification debug consisted primarily of comprehending the structure and source code of the design with waveforms showing activity over time, based ...

SANTA CRUZ, Calif. — To help IC verification teams work with blocks that conform to the Open Core Protocol, the OPC International Partnership (OCP-IP) has released a set of functional coverage ...